The Federal Communications Commission (FCC) has allotted a spectrum of bandwidth in the 60 GHz frequency range (57 to 64 GHz). The Wireless Gigabit Alliance (WiGig) targets the standardization of this frequency band that will support data transmission rates up to 7 Gbps. Integrated circuits, formed in semiconductor die, offer high frequency operation in this millimeter wavelength range of frequencies. Some of these integrated circuits utilize Complementary Metal Oxide Semiconductor (CMOS), Silicon-Germanium (SiGe) or GaAs (Gallium Arsenide) technology to form the dice in these designs.
CMOS (Complementary Metal Oxide Semiconductor) is the primary technology used to construct integrated circuits. N-channel transistors and P-channel transistors (MOS transistor) are used in this technology which uses fine line technology to consistently reduce the channel length of the MOS transistors. Current channel length examples are 40 nm, the power supply of VDD equals 1.2V and the number of layers of metal levels can be 8 or more. This technology typically scales with technology and can achieve operation in the 60 GHz range.
Transceivers for the 60 GHz system have been formed in CMOS and comprise at least one transmitter and at least one receiver which are used to interface to other transceivers in a communication system. The transceivers receive or transmit electrical signals into the LNA or the power amplifier, respectively. These electrical signals are generated by or provided to an antenna. The antenna is a transducer that converts incoming electromagnetic energy from free space into electrical signals on the receive side of the transceiver or converts electrical signals into electromagnetic energy for transfer into free space.
Conventionally, the design of circuits at 60 GHz requires careful layout. One traditional way to distribute a 60 GHz clock is to use transmission line based power splitters and quadrature hybrids whose size are proportional to a quarter wavelength (˜600 um). Therefore, the entire distribution network occupies significant area if the circuit components are formed using transmission lines (for example, see the passive power splitter in FIG. 7 of Alberto Valdes-Garcia, et al. “A Fully Integrated 16-Element Phased-Array Transmitter in SiGe BiCMOS for 60-GHz Communications” IEEE J. Solid-State Circuits, vol. 45, no. 12, pp. 2757-2773, December 2010 and see the quadrature hybrid layout in FIG. 9 of C. Marcu et al., “A 90 nm CMOS low-power 60-GHz transceiver with integrated baseband circuitry,” IEEE J. Solid-State Circuits, vol. 44, no. 12, pp. 3434-3447, December 2009). The in-phase clock and quadrature phase clock are applied to these circuit components as these clocks are routed on the surface of the die. Furthermore, the routing from, around and between these circuit components requires power to be dissipated for each interconnect of the in-phase clock and quadrature phase clock traces. In addition, the layout needs to allow the in-phase clock and quadrature phase clock to maintain their 90° separation as these clocks are routed from the source location to their destination location. To overcome this shortcoming, a solution is herein provided that reduces the power dissipation and area of routing these clock lines on a semiconductor die.
As mentioned above, some circuit components required in multi-tens of GHz clock network distribution designs have been fabricated using transmission lines on the die. However, these circuit components formed on the die would use up valuable real-estate on the semiconductor substrate. For example, a quarter wavelength at 60 GHz is 0.6 mm which is a length that may equal the width of a semiconductor die. Thus, the integration of these transmission line circuit components into the semiconductor die would use a significant portion of the area of the die. A solution to reduce the real estate of these circuit components integrated on a die is provided to overcome this shortcoming.
The transmitter needs to provide a signal to the antenna consisting of the fundamental frequency. Furthermore, the power amplifier (PA) in the transmitting circuit should be designed to minimize power dissipation and maximize the energy transfer to the antenna. In addition, the power amplifier to perform these functions should minimize transistor usage particularly cascode-like structures since the available head room is only about 500-600 mV which is about half of the 1.2V power supply. A solution to maximize energy transfer and minimize second order harmonics from appearing at the output of the power amplifier is provided to overcome this shortcoming.
Second harmonics due to the non-linear behavior of the transistor introduces an additional difficulty in power amplifier design. These second harmonics can distort the desired waveform at the antenna and reduce the purity of the desired signal being transferred. Several solutions are presented to remove these second order distortions as well as using them advantageously to improve the quality of the signal being delivered to the antenna.
The transmitters and receivers for the 60 GHz radio system can be coupled to form a SIMO (Single Input Multiple Output) system. This system would use more than one antenna at the transmitter to steer the beam to an antenna located on the receiver. The outputs generated from the multiple output antennas will be received by the single receive antenna and provide an increased data throughput and link range without increasing the total output power or signal bandwidth.
The transceivers and receivers for the 60 GHz radio system can be coupled to form a MIMO (Multiple Input Multiple Output) system. This system would use more than one antenna at the transmitter and more than one antenna for the receiver. The outputs generated from the multiple output antennas will be received by the multiple receiver antennas providing increased data throughput and link range without increasing the total output power or signal bandwidth.